Addressing Modes

Addressing modes define how the processor accesses data. There are 15 different addressing modes, such as: Direct Addressing, Indirect Addressing, Indirect with Displacement, Immediate Addressing, Register Addressing, Relative Addressing, Indirect I/O Addressing, and Stack Addressing.

Details on addressing modes are presented in Fig. 1,2,3,4,5,6,7,8,9,10,11,12,13 and 14:

1. Direct Single Register Addressing

Direct Single Register Addressing
Figure 1: Direct Single Register Addressing

The operand is contained in the destination register (Rd).

2. Direct Register Addressing, Two Registers

Direct Register Addressing, Two Registers
Figure 2: Direct Register Addressing, Two Registers

Operands are contained in the source register (Rr) and destination register (Rd). The result is stored in the destination register (Rd).

3. I/O Direct Addressing

I/O Direct Addressing
Figure 3: I/O Direct Addressing

Operand address A is contained in the instruction word. Rr/Rd specifies the destination or source register.

4. Data Direct Addressing

Data Direct Addressing
Figure 4: Data Direct Addressing

A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. The LDS instruction uses the RAMPD register to access memory above 64 KB.

5. Data Indirect Addressing

Data Indirect Addressing
Figure 5: Data Indirect Addressing

The operand address is the contents of the X-, Y-, or Z-pointer. In AVR devices without SRAM, Data Indirect Addressing is called Register Indirect Addressing.

6. Data Indirect Addressing with Pre-decrement

Data Indirect Addressing with Pre-decrement
Figure 6: Data Indirect Addressing with Pre-decrement

The X,- Y-, or the Z-pointer is decremented before the operation. The operand address is the decremented contents of the X-, Y-, or Z-pointer.

7. Data Indirect Addressing with Post-increment

Data Indirect Addressing with Post-increment
Figure 7: Data Indirect Addressing with Post-increment

The X-, Y-, or Z-pointer is incremented after the operation. The operand address is the content of the X-, Y-, or Z-pointer before incrementing.

8. Data Indirect with Displacement

Data Indirect with Displacement
Figure 8: Data Indirect with Displacement

The operand address is the result of the q displacement contained in the instruction word added to the Y- or Z-pointer. Rd/Rr specify the destination or source register.

9. Program Memory Constant Addressing

Program Memory Constant Addressing
Figure 9: Program Memory Constant Addressing

The byte address in program memory is determined by the value stored in the Z-pointer.

The upper 15 bits (Most Significant bits - MSbs) select the word address (each word contains 2 bytes).

The lowest bit (Less Significant bit - LSb) selects which byte of that word is used:

For the SPM instruction, the LSb must be 0, because SPM works on whole words. SPM (Store Program Memory) is an instruction used in AVR microcontrollers to write data into program memory (Flash). Normally, Flash is read‑only during program execution, but SPM allows the microcontroller to modify or update its own program, for example inside a bootloader.

When the ELPM instruction is used, the RAMPZ register provides extra address bits so the processor can access larger program memories. ELPM (Extended Load Program Memory) is an instruction used to read bytes from program memory when the memory is larger than 64 KB. The normal LPM instruction can only access 64 KB because it uses the 16‑bit Z register. ELPM adds extra address bits from the RAMPZ register, allowing access to extended program memory on larger AVR devices.

In short: ELPM = LPM with support for large program memory using RAMPZ.

10. Program Memory Addressing with Post-increment [pczekalski]Continue figures formatting here [mfojcik]Marcin, czy tu nie brakuje rysunku? The Z-pointer contents specify a constant byte address. The 15 MSbs select the word address. The LSb selects the low byte if cleared (LSb == 0) or the high byte if set (LSb == 1). If ELPM Z+ is used, the RAMPZ Register is used to extend the Z-register.

11. Store Program Memory [mfojcik]Marcin, tu mam wątpliwości co do nazwy tego rozdziału - to addressing mode?

Store Program Memory
Figure 10: Store Program Memory

The Z-pointer is incremented by 2 after the operation. The Z-pointer contents specify a constant byte address before incrementing. The 15 MSbs select the word address, and the LSb should be left cleared.

12. Direct Program Memory Addressing

Direct Program Memory Addressing
Figure 11: Direct Program Memory Addressing

Program execution continues at the address immediate in the instruction word. [mfojcik] "immediate" -> "following immediately the instruction word"?

13. Indirect Program Memory Addressing

Indirect Program Memory Addressing
Figure 12: Indirect Program Memory Addressing

Program execution continues at the address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).

14. Extended Indirect Program Memory Addressing

Extended Indirect Program Memory Addressing
Figure 13: Extended Indirect Program Memory Addressing

Program execution continues at the address contained by the Z-register and the EIND-register (i.e., the PC is loaded with the contents of the EIND and Z-register).

15. Relative Program Memory Addressing

Relative Program Memory Addressing
Figure 14: Relative Program Memory Addressing

Program execution continues at the address PC + k + 1. The relative address k is from -2048 to 2047.