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| + | ======ESP32-Cx Family====== | ||
| + | {{: | ||
| + | ==ESP32-C2 General Information== | ||
| + | |||
| + | The ESP32-C2 (ESP8684) ((https:// | ||
| + | |||
| + | The ESP32-C2 microcontrollers come with several distinctive features: | ||
| + | * RISC-V Core: The ESP32-C2 is based on the RISC-V architecture, | ||
| + | * Connectivity: | ||
| + | * Low Power Consumption: | ||
| + | * Rich Peripheral Interface Support: It includes a variety of peripherals such as UART, I2C, SPI, ADC, and more, making it versatile for different applications. | ||
| + | * Security Features: The ESP32-C2 family includes various security features, such as secure boot, flash encryption, secure storage, and cryptographic accelerators. | ||
| + | * Compact Form Factor: The ESP32-C2 family is designed in a very compact form factor (4mm x 4mm), which is crucial for applications with limited space or miniaturization. | ||
| + | * Cost-Effective Solution: These microcontrollers offer a cost-effective solution for IoT applications without compromising essential features and performance. | ||
| + | |||
| + | For now the ESP32-C2 family includes the following chips in mass production (figure {{ref> | ||
| + | * ESP8684. | ||
| + | |||
| + | <figure esp32_c2> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | ===== ESP32-C2 ===== | ||
| + | |||
| + | == ESP32-C2 Architecture Overview == | ||
| + | Figure {{ref> | ||
| + | |||
| + | **Processors** | ||
| + | * **Main processor: | ||
| + | * **Cores**: 1 up to 120 MHz, | ||
| + | * External main crystal clock, | ||
| + | * External 32 kHz crystal oscillator for RTC or internal RC. | ||
| + | |||
| + | **Wireless connectivity** | ||
| + | * **WiFi:** 802.11 b/g/n (802.11n @ 2.4 GHz up to 72.2 Mbit/s) with simultaneous Infrastructure BSS Station mode/ | ||
| + | * **Bluetooth: | ||
| + | |||
| + | **Memory: Internal memory** | ||
| + | * **Embedded flash** | ||
| + | * **ROM:** 576 kB (for booting and core functions), | ||
| + | * **SRAM:** 272 kB (16kB for cache), | ||
| + | * ** eFuse ** - 1 Kbit -256 bits reserved for encryption key and device ID. | ||
| + | |||
| + | **Peripheral Input/ | ||
| + | * 14 x GPIO, | ||
| + | * 3 × SPI (Serial Peripheral Interface), | ||
| + | * 2 x UART (universal asynchronous receiver/ | ||
| + | * 1 × I²C Master (Inter-Integrated Circuit), | ||
| + | * LED PWM up to 6 channels, | ||
| + | * 1 x 12-bit ADCs (analogue-to-digital converter) up to 5 channels, | ||
| + | * General DMA controller (GDMA), with 1 transmit channel and 1 receive channel. | ||
| + | |||
| + | ** Power Modes ** | ||
| + | * Active Mode, | ||
| + | * Modem-sleep mode, | ||
| + | * Light-sleep mode, | ||
| + | * Deep-sleep mode. | ||
| + | |||
| + | **Security** | ||
| + | * Secure boot, | ||
| + | * Flash encryption, | ||
| + | * 1024-bit OTP, up to 256-bit for customers, | ||
| + | * Cryptographic hardware acceleration: | ||
| + | * SHA1/ | ||
| + | * ECC, | ||
| + | * random number generator (RNG), | ||
| + | * clock glitch filter. | ||
| + | |||
| + | <figure esp32c2_functions> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | For now the ESP32-C2 family includes the following chips in mass production (table {{ref> | ||
| + | |||
| + | <table esp32c2_chips> | ||
| + | < | ||
| + | ^**Module**^**Chip Embedded**^**Dimensions (mm)**^**Pins**^**GPIO**^**Flash (MB)**^**PSRAM (MB)**^**Antenna type**^**Development Board**^ | ||
| + | | {{ : | ||
| + | |{{ : | ||
| + | |{{ : | ||
| + | |{{ : | ||
| + | |{{ : | ||
| + | |{{ : | ||
| + | |{{ : | ||
| + | |{{ : | ||
| + | |{{ : | ||
| + | |{{ : | ||
| + | | ||
| + | - **Note** 1: When surface mounted, the module has 14 available GPIOs; when vertically soldered, the module has 5 available GPIOs. \\ | ||
| + | </ | ||
| + | |||
| + | ===== ESP32-C3 ===== | ||
| + | |||
| + | ==ESP32-C3 General Information== | ||
| + | |||
| + | The ESP32-C3 family is a series of microcontrollers developed by Espressif Systems. It's based on the RISC-V architecture and is designed to offer low-power and cost-effective solutions for various IoT (Internet of Things) applications. These chips integrate WiFi connectivity, | ||
| + | |||
| + | The ESP32-C3 microcontrollers come with several distinctive features: | ||
| + | |||
| + | * RISC-V Core: One of the notable aspects of the ESP32-C3 family is the use of the RISC-V instruction set architecture, | ||
| + | * WiFi Connectivity: | ||
| + | * Low Power Consumption: | ||
| + | * Rich Peripheral Interface Support: The microcontrollers have various peripheral interfaces, such as SPI, I2C, UART, PWM, and ADC. These interfaces allow easy integration with multiple sensors, displays, and other devices, enhancing the versatility of applications that can be developed. | ||
| + | * Security Features: The ESP32-C3 family includes various security features like secure boot, flash encryption, secure storage, and cryptographic accelerators. These elements contribute to the overall security of the devices developed using these microcontrollers. | ||
| + | * Compact Form Factor: The ESP32-C3 family is designed in a compact form factor, which is advantageous for applications where limited space or miniaturization is a concern. | ||
| + | * Cost-Effective Solution: These microcontrollers offer a cost-effective solution for IoT applications without compromising essential features and performance. | ||
| + | |||
| + | For now the ESP32-C3 family includes the following chips in mass production (table {{ref> | ||
| + | |||
| + | <table esp32c3_chips> | ||
| + | < | ||
| + | |||
| + | ^**SoC**^**Variants**^**Core**^**Dimensions (mm)**^**Pins**^**RAM (kB)**^**Flash (MB)**^**PSRAM (MB)**^ | ||
| + | |ESP32-C3(figure {{ref> | ||
| + | |ESP8686(figure {{ref> | ||
| + | |ESP8685(figure {{ref> | ||
| + | \\ | ||
| + | </ | ||
| + | |||
| + | |||
| + | <figure esp32_c3> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | <figure esp8686> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | <figure esp8685> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | |||
| + | == ESP32-C3 Architecture Overview == | ||
| + | Figure {{ref> | ||
| + | |||
| + | **Processors** | ||
| + | * **Main processor: | ||
| + | * **Cores**: 1 up to 160 MHz, | ||
| + | * External main crystal clock, | ||
| + | * External 32 kHz crystal oscillator for RTC or internal RC. | ||
| + | |||
| + | **Wireless connectivity** | ||
| + | * **WiFi:** 802.11 b/g/n (802.11n @ 2.4 GHz up to 150 Mbit/s) with simultaneous Infrastructure BSS Station mode/ | ||
| + | * **Bluetooth: | ||
| + | |||
| + | **Memory: Internal memory** | ||
| + | * **Embedded flash** | ||
| + | * **ROM:** 384 kB (for booting and core functions). | ||
| + | * **SRAM:** 400 kB (16kB for cache). | ||
| + | * **RTC fast SRAM:** 8 kB | ||
| + | * ** eFuse ** - 4 Kbit - 1792 bits reserved for encryption key and device ID | ||
| + | |||
| + | **Peripheral Input/ | ||
| + | * 22 or 16 GPIO | ||
| + | * 2 x 12-bit ADCs (analog-to-digital converter) up to 6 channels, | ||
| + | * General DMA controller (GDMA), with 3 transmit channels and 3 receive channels, | ||
| + | * 1 × I²C (Inter-Integrated Circuit), | ||
| + | * 2 x UART (universal asynchronous receiver/ | ||
| + | * 1 × TWAI® controller compatible with ISO 11898-1 (CAN Specification 2.0), | ||
| + | * 3 × SPI (Serial Peripheral Interface), | ||
| + | * 1 × I²S (Integrated Inter-IC Sound), | ||
| + | * LED PWM up to 6 channels, | ||
| + | * Internal temperature sensor, | ||
| + | * USB Serial/JTAG controller. | ||
| + | |||
| + | **Security** | ||
| + | * Secure boot, | ||
| + | * Flash encryption, | ||
| + | * 4096-bit OTP, up to 1792-bit for customers, | ||
| + | * Cryptographic hardware acceleration: | ||
| + | * AES-128/ | ||
| + | * SHA accelerator, | ||
| + | * RSA accelerator, | ||
| + | * random number generator (RNG), | ||
| + | * digital signature. | ||
| + | |||
| + | <figure esp32c3_functions> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | ==ESP32-C3 Modules== | ||
| + | Espressif also produces modules that are more integrative and more convenient for amateurs and developers to use. The following modules are currently available: | ||
| + | * ESP32-C3-Mini-1/ | ||
| + | * ESP32-C3-WROOM-02/ | ||
| + | |||
| + | | ||
| + | <figure esp32_c3_mini1> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | | ||
| + | <figure esp32_c3_wroom> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | |||
| + | ==ESP32-C3 Development Kits== | ||
| + | Development kits are the most convenient for quick application or to check the capabilities of processors. Espressif manufactures them and many companies specialising in producing prototype circuits. The following are some of the most versatile modules | ||
| + | * Espressif - ESP32-C3-DevkitM-1((https:// | ||
| + | * Espressif - ESP32-C3-DevkitC-02((https:// | ||
| + | * Espressif - ESP32-C3-LCDKit ((https:// | ||
| + | * Adafruit - QT Py ESP32-C3 WiFi Dev Board with STEMMA QT((https:// | ||
| + | * Seeed Studio - XIAO ESP32C3 ((https:// | ||
| + | * M5stack - M5Stamp-C3 ((https:// | ||
| + | |||
| + | <figure esp32_c3_devkitm> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | <figure esp32_c3_devkitc> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | <figure esp32_c3_devkitlcd> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | <figure esp32_c3_adafruit> | ||
| + | {{ : | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | <figure esp32_xiao> | ||
| + | {{ : | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | <figure esp32_stampc3> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | < | ||
| + | |||
| + | == ESP32-C3 chip comparison == | ||
| + | The Esp32-C3 as a more modern one, can successfully replace the oldest family of ESP8266 chips, so table {{ref> | ||
| + | |||
| + | <table esp32c3> | ||
| + | < | ||
| + | \\ | ||
| + | ^**Feature**^**ESP8266**^**ESP32-C3 Series**^ | ||
| + | |Launch year|2014|2020| | ||
| + | |Core|Xtensa® single core 32-bit LX6|32-bit single-core RISC-V| | ||
| + | |Wi-Fi protocols|802.11 b/g/, 2.4 GHz up to 72.2. Mbps|802.11 b/g/n, 2.4 GHz up to 150 Mbps| | ||
| + | |Bluetooth®| ✖️|Bluetooth 5.0| | ||
| + | |Typical frequency|80 MHz |160 MHz| | ||
| + | |SRAM|160kB|400 KB| | ||
| + | |ROM|384 KB |384 KB for booting and core functions| | ||
| + | |Embedded flash|✖️|4 MB or none, depending on variants| | ||
| + | |RTC memory|768B|8kB| | ||
| + | |Cache |32KB instruction|16kB| | ||
| + | |PMU|✔️|✔️| | ||
| + | |**Peripherals**| | ||
| + | |ADC|10-bit|Two 12-bit SAR ADCs, at most 6 channels| | ||
| + | |DAC|✖️|✖️| | ||
| + | |Timers|2 x 23 - bit|Two 54-bit general-purpose timers, and three watchdog timers| | ||
| + | |Temperature sensor|1|1| | ||
| + | |Touch sensor|✖️|✖️| | ||
| + | |Hall sensor|✖️|✖️| | ||
| + | |GPIO|17|22| | ||
| + | |SPI|2|3| | ||
| + | |LCD interface|✖️|✖️| | ||
| + | |UART|2 – One Tx only|2 | | ||
| + | |I2C|1- | ||
| + | |I2S|1 |1, can be configured to operate with 8/ | ||
| + | |Camera interface|✖️|✖️| | ||
| + | |DMA|✖️|General-purpose, | ||
| + | |RMT|1 x TX + 1 x RX|4 channels < | ||
| + | |Pulse counter|✖️|✖️| | ||
| + | |LED PWM|5 channels|6 channels| | ||
| + | |PWM|✖️/ | ||
| + | |TWAI® controller (compatible with ISO 11898-1)|✖️|1| | ||
| + | |SD/ | ||
| + | |SDIO slave controller|✖️|✖️| | ||
| + | |Ethernet MAC|✖️|✖️| | ||
| + | |Debug Assist JTAG|✖️|1| | ||
| + | |**Security**| | ||
| + | |Secure boot|✖️|✔️ Faster and safer, compared with ESP32, | ||
| + | |Flash encryption|✖️|✔️ Safer, compared with ESP32, XTS-AES-128| | ||
| + | |OTP|1024-bit|4096-bit| | ||
| + | |AES|✖️|✔️ AES-128, AES-256 (FIPS PUB 197); DMA support| | ||
| + | |HASH|SHA-1, | ||
| + | |RSA|Up to 4096 bits|Up to 3072 bits| | ||
| + | |RNG|✔️|✔️| | ||
| + | |HMAC|✖️|✔️| | ||
| + | |Digital signature|✖️|✔️| | ||
| + | |XTS|✖️|✔️ XTS-AES-128| | ||
| + | |**Other**| | ||
| + | |Light sleep |2 mA|130μA| | ||
| + | |Deep Sleep|20 μA|5 μA| | ||
| + | |Hibernation|-|-| | ||
| + | |Power off|0.5 μA|1μA| | ||
| + | |Size|QFN32 5*5|QFN32 5*5| | ||
| + | \\ | ||
| + | </ | ||
| + | |||
| + | ===== ESP32-C6 ===== | ||
| + | |||
| + | ==ESP32-C6 General Information== | ||
| + | ESP32-C6 is Espressif' | ||
| + | |||
| + | == ESP32-C6 Architecture Overview == | ||
| + | Figure {{ref> | ||
| + | |||
| + | **Processors** | ||
| + | * **Main processor: | ||
| + | * **Cores**: 1, | ||
| + | * External main crystal clock, | ||
| + | * External 32 kHz crystal oscillator for RTC or internal RC. | ||
| + | * **Low-power processor: | ||
| + | * **Cores**: 1, | ||
| + | * External main crystal clock, | ||
| + | * External 32 kHz crystal oscillator for RTC or internal RC. | ||
| + | |||
| + | **Wireless connectivity** | ||
| + | * **WiFi: | ||
| + | * ** WiFI: | ||
| + | * **Bluetooth: | ||
| + | * **IEEE 802.15.4-2015: | ||
| + | |||
| + | **Memory: Internal memory** | ||
| + | * **Embedded flash** | ||
| + | * **ROM:** 320 kB (booting and core functions), | ||
| + | * **HP SRAM:** 510 kB, | ||
| + | * ** LP SRAM:** 16 kB, | ||
| + | * **RTC fast SRAM:** 8 kB, | ||
| + | * ** eFuse ** - 4 Kbit - 1792 bits reserved for encryption key and device ID. | ||
| + | |||
| + | **Peripheral Input/ | ||
| + | * 30xGPIO (QFN40) or 22xGPIO (QFN32), | ||
| + | * General DMA controller (GDMA), with 3 transmit channels and 3 receive channels, | ||
| + | * 1 × I²C (Inter-Integrated Circuit), | ||
| + | * 2 x UART, | ||
| + | * 1 x Low-Power UART, | ||
| + | * 2 × TWAI® controller compatible with ISO 11898-1 (CAN Specification 2.0), | ||
| + | * 2 × SPI (Serial Peripheral Interface for flash), | ||
| + | * 1 × SPI (Serial Peripheral Interface universal ), | ||
| + | * 1 × I²S (Integrated Inter-IC Sound), | ||
| + | * 1 × SDIO 2.0 slave controller, | ||
| + | * 1 × Motor Control PWM (MCPWM), | ||
| + | * LED PWM up to 6 channels, | ||
| + | * 1 x USB Serial/JTAG controller, | ||
| + | * 1 x Remote control peripheral (TX/RX), | ||
| + | * 1 x Parallel IO interface (PARLIO), | ||
| + | * 1 x 12-bit SAR ADCs (analog-to-digital converter) up to 7 channels, | ||
| + | * 1 x temperature sensor. | ||
| + | |||
| + | **Security** | ||
| + | * Secure boot, | ||
| + | * Flash encryption, | ||
| + | * External Memory Encryption and Decryption (XTS_AES), | ||
| + | * 4096-bit OTP, up to 1792-bit for customers, | ||
| + | * Trusted execution environment (TEE) controller and access permission management (APM), | ||
| + | * Cryptographic hardware acceleration: | ||
| + | * AES-128/ | ||
| + | * ECC, | ||
| + | * SHA accelerator, | ||
| + | * RSA accelerator, | ||
| + | * HASH (FIPS PUB 180-4), | ||
| + | * random number generator (RNG), | ||
| + | * digital signature. | ||
| + | |||
| + | <figure esp32c6_functions> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | ==ESP32-C6 Modules== | ||
| + | The following modules are currently available (table {{ref> | ||
| + | |||
| + | <table esp32c6_modules> | ||
| + | < | ||
| + | ^**Module**^**Chip embedded**^**Dimensions (mm)**^**Pins**^**Development board**^ | ||
| + | |ESP32-C6-Mini-1/ | ||
| + | |ESP32-C6-WROOM-02/ | ||
| + | |||
| + | </ | ||
| + | |||
| + | <figure esp32_c6_mini1> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | | ||
| + | <figure esp32_c6_wroom> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | ==ESP32-C6 Development Boards== | ||
| + | There are not many prototype kits with ESP32-C6 SOCs on the market yet. Two sets released by the manufacturer deserve special attention. They are both entry-level development boards: | ||
| + | * Espressif - ESP32-C6-DevkitM-1 ((https:// | ||
| + | * Espressif - ESP32-C6-DevkitC-1((https:// | ||
| + | |||
| + | <figure esp32_c6_devkitm> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | | ||
| + | <figure esp32_c6_devkitc> | ||
| + | {{ : | ||
| + | < | ||
| + | </ | ||
| + | |||
| + | They allow you to test all processor functions, including WiFi, Bluetooth LE, Zigbee, and Thread. | ||
| + | |||
| + | <note important> | ||
| + | </ | ||