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--- en:iot-open:hardware2:esp32s [2023/11/05 11:53] – jpaduch
+++ en:iot-open:hardware2:esp32s [2024/05/27 14:15] (current) – pczekalski
@@ Line 1: / Line 1: @@
+======ESP32-Sx Family======
+{{:en:iot-open:czapka_b.png?50| General audience classification icon }}{{:en:iot-open:czapka_e.png?50| General audience classification icon }}\\
+===== ESP32-S2 =====
+==ESP32-S2 General Information==
+The Espressif ESP32-S2 family is a series of low-power, single-core microcontrollers built on the Espressif IoT platform. They feature a highly integrated SoC (System on Chip) architecture, combining a CPU, WiFi connectivity, and various peripherals in a compact package. The ESP32-S2 chips are designed for IoT applications, smart home devices, wearables and more, offering enhanced security features, low power consumption, and support for various communication protocols. These microcontrollers are known for their cost-effectiveness and capabilities of connected devices. ESP32-S2 SoC is based on an Xtensa single-core 32-bit LX7 microcontroller with an additional ultra-low power (ULP) coprocessor with a Wi-Fi 2.4GHz  radio and numerals peripherals.
+For now, the ESP32-S2 series includes the following chips in mass production:
+  *  ESP32-S2 (figure {{ref>esp32_s2}}) , \\
+  *  ESP32-S2F (figure {{ref>esp32_s2f}}) . \\
+<figure esp32_s2>
+{{ :en:iot-open:hardware2:esp32s2.png?100 | ESP32-S2}}
+<caption>ESP32-S2</caption>
+</figure>
+<figure esp32_s2f>
+{{ :en:iot-open:hardware2:esp32s2f.png?100 | ESP32-S2F}}
+<caption>ESP32-S2F</caption>
+</figure>
+== ESP32-S2 Architecture Overview ==
+Figure {{ref>esp32s2_functions}} shows functional block diagram of ESP32-S2 chip((https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)). The main common features of the ESP32-S2 are:
+**Processors**
+    *  **Main processor:** • Xtensa® single-core 32-bit LX7 microprocessor, up to 240 MHz
+      *  **Cores**: 1
+    * **Ultra low power coprocessor:**
+      * **Cores**: 1
+**Wireless connectivity**
+    *  **WiFi:** 802.11 b/g/n/(802.11n @ 2.4 GHz up to 150 Mbit/s) with simultaneous Infrastructure BSS Station mode/SoftApp mode/Promiscuous mode.
+**Memory: Internal memory**
+      *  **ROM:** 128 kB (for booting and core functions),
+      *  **SRAM:** 320 kB (for data and instruction),
+      *  **RTC SRAM:** 16 kB (for data storage and main CPU during RTC Boot from the deep-sleep mode),
+      *  **Embedded flash:**
+           * 0 MB (ESP32-S2, ESP32-S2R2 chips),
+           * 2 MB (ESP32-S2FH2 chip),
+           * 4 MB (ESP32S2FH4, ESP32FN4R2 chips).
+      * **Embedded PSRAM:**
+           * 0 MB (ESP32-S2, ESP32-S2FH2, ESP32S2FH4 chips ),
+           * 2 MB (ESP32FN4R2, ESP32-S2R2 chips ).
+**Peripheral Input/Output**
+    * 43 programmable GPIOs,
+    * 2 × I²C (Inter-Integrated Circuit,
+    * 2 x UART (universal asynchronous receiver/transmitter),
+    * 4 × SPI (Serial Peripheral Interface),
+    * 1 × I²S (Integrated Inter-IC Sound),
+    * 1 x RMT (TX/RX),
+    * Motor PWM (pulse width modulation),
+    * LED PWM up to 8 channels,
+    * DMA controller,
+    * 1 x TWAI controller compatible with CAN Spec. 2.0,
+    * 4 x pulse counters,
+    * 1 x full-speed USB OTG,
+    * 1 x DVP 8/16 camera interface (I2S),
+    * 1 x LCD serial interface (SPI),
+    * 1 x LCD parallel interface.
+**Analog interfaces**
+    * 2 x 13-bit ADCs up to 20 channels,
+    * 2 x 8-bit DACs,
+    * 14 x touch sensing GPIO,
+    * 1 x temperature sensor.
+**Security**
+    *  Secure boot,
+    *  Flash encryption,
+    *  IEEE 802.11 standard security features are all supported, including WFA, WPA/WPA2 and WAPI,
+    *  4096-bit OTP, up to 1792-bit for customers,
+    *  Cryptographic hardware acceleration:
+      * AES-128/192/256,
+      * HMAC,
+      * RSA,
+      * random number generator (RNG).
+<figure esp32s2_functions>
+{{ :en:iot-open:hardware2:esp32s2block.png?200 | ESP32-S2 Functional block diagram}}
+<caption>ESP32-S2 Functional block diagram</caption>
+</figure>
+== ESP32-S2 Modules ==
+The company also produces ready-made modules for easier implementation in user systems. These modules combines ESP32-S2 microcontroller and additional components mounted on PCB with EM shield ((https://www.espressif.com/en/products/modules))(table {{ref>esp32s2_modules}}):
+<table esp32s2_modules>
+<caption>Espressif ESP32-S2 modules</caption>
+^ **Module**                                        ^ **Chip Embedded**              ^ **Dimensions (mm)**  ^ **Pins**  ^ **Flash (MB)**  ^ **PSRAM (MB)**  ^ **Antenna**  ^ **Development Board**  ^
+| ESP32-S2-MINI-2 (figure {{ref>esp32_S2_mini2}})   | ESP32-S2FH4 \\  ESP32-S2FN4R2  | 15.4×20×2.4          | 65        | 4               | 0,2             | PCB          | ESP32-S2-DevKitM-1     |
+| ESP32-S2-MINI-2U                                  | ESP32-S2FH4 \\  ESP32-S2FN4R2  | 15.4×15.4×2.4        | 65        | 4               | 0,2             | IPEX         | ESP32-S2-DevKitM-1     |
+| ESP32-S2-SOLO-2 (figure {{ref>esp32_S2_solo2}})   | ESP32-S2 \\ ESP32-S2R2         | 18x25.5x3.1          | 41        | 4               | 0,2             | PCB          | ESP32-S2-DevKitC-1     |
+| ESP32-S2-SOLO-2U                                  | ESP32-S2 \\  ESP32-S2R2        | 18×19.2×3.2          | 41        | 4               | 0,2             | IPEX         | ESP32-S2-DevKitC-1     |
+| ESP32-S2-MINI-1                                   | ESP32-S2FH4 \\ ESP32-S2FN4R2   | 15.4×20×2.4          | 65        | 4               | 0,2             | PCB          | ESP32-S2-DevKitM-1     |
+| ESP32-S2-MINI-1U (figure {{ref>esp32_S2_mini1}})  | ESP32-S2FH4 \\ ESP32-S2FN4R2   | 15.4×15.4×2.4        | 65        | 4               | 0,2             | IPEX         | ESP32-S2-DevKitM-1     |
+| ESP32-S2-SOLO                                     | ESP32-S2 \\ ESP32-S2R2         | 18×25.5×3.1          | 40        | 4,8,16          | 0,2             | PCB          | ESP32-S2-DevKitC-1     |
+| ESP32-S2-SOLO-U                                   | ESP32-S2 \\ ESP32-S2R2         | 18×19.2×3.2          | 40        | 4,8,16          | 0,2             | IPEX         | ESP32-S2-DevKitC-1     |
+</table>
+<figure esp32_S2_mini2>
+{{ :en:iot-open:hardware2:esp32s2mini2.png?100 | ESP32-S2-mini2}}
+<caption>ESP32-S2-mini2</caption>
+</figure>
+<figure esp32_S2_solo2>
+{{ :en:iot-open:hardware2:esp32s2solo.png?100 | ESP32-S2-solo2}}
+<caption>ESP32-S2-solo2</caption>
+</figure>
+<figure esp32_S2_mini1>
+{{ :en:iot-open:hardware2:esp32s2mini1.png?100 | ESP32-S2-mini-1U}}
+<caption>ESP32-S2-mini-1U</caption>
+</figure>
+== ESP32-S2 Development Kits ==
+For convenience, used by users of all skill levels, Espressif produces entry-level development boards using the ESP32-S2 SOCs. Those boards integrate complete Wi-Fi functions. Most ESP32-S2 I/O pins are broken out to the pin headers on both sides for easy interfacing. Users can connect peripherals with jumper wires or mount the development kit on a breadboard. Many different companies offer ready-made boards with processors. The original Espressif best-known small development boards are:
+  *  ESP32-S2-DevkitM ((https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-devkitm-1-v1.html))(figure {{ref>esp32_S2_devkitm}}) , \\
+  *  ESP32-S2-DevkitC ((https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-s2-devkitc-1.html))(figure {{ref>esp32_S2_devkitc}}) , \\
+<figure esp32_S2_devkitm>
+{{ :en:iot-open:hardware2:esp32-s2-devkitm-1-v1-annotated-photo.png?400 | ESP32-S2-DevkitM}}
+<caption>ESP32-S2-DevkitM</caption>
+</figure>
+<figure esp32_S2_devkitc>
+{{ :en:iot-open:hardware2:esp32-s2-devkitc-1-v1-annotated-photo.png?400 | ESP32-S2-DevkitC}}
+<caption>ESP32-S2-DevkitC</caption>
+</figure>
+===== ESP32-S3 =====
+== ESP32-S3 General Information ==
+The ESP32-S3((https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf))((https://www.espressif.com/sites/default/files/documentation/esp32-s3-pico-1_datasheet_en.pdf)) is an advanced version within Espressif S family, offering improved performance and expanded capabilities compared to its predecessors. ESP32-S3 is an MCU with a dual-core 32-bit Xtensa LX7 microprocessor, dual ULP coprocessors with Wifi 2.4 GHz and Bluetooth LE radio, and numerous useful peripherals. ESP32-S3 offers enhanced processing power, lower power consumption, and improved IoT and wireless connectivity application features. ESP32-S3 is designed for mobile systems, Industrial and Home Automation, Health Care devices, Touch and Proximity Sensing, wearable electronics, and Internet-of-Things (IoT) applications. In addition, ESP32-S3 includes support for vector instructions in the MCU, which provides acceleration for neural network computing and signal processing workloads. The ESP32-S3 is the first low-cost microcontroller with a built-in peripheral that can drive TTL displays, and it can come with enough PSRAM to buffer those large images. For now, the ESP32-S3 family includes the following chips in mass production:
+  *  ESP32-S3 (figure {{ref>esp32_s3}}) , \\
+  *  ESP32-S3-Pico-1 (figure {{ref>esp32_s3pico1}}). \\
+<figure esp32_s3>
+{{ :en:iot-open:hardware2:esp32s3.png?100 | ESP32-S3}}
+<caption>ESP32-S3</caption>
+</figure>
+<figure esp32_s3pico1>
+{{ :en:iot-open:hardware2:esp32s3pico1.png?100 | ESP32-S3-PICO-1}}
+<caption>ESP32-S3-PICO-1</caption>
+</figure>
+== ESP32-S3 Architecture Overview ==
+Figure {{ref>esp32s3_functions}} shows a functional block diagram of the ESP32-S3 chip. ESP32-S3's main common features of the ESP32-S3 are:
+**Processors**
+    *  **Main processor:** • Xtensa® dual-core 32-bit LX7 microprocessor, up to 240 MHz:
+      *  **Cores**: 2
+    * **Ultra low power coprocessor:**
+      * **Cores**: 2
+      * ULP-RISC-V coprocessor - based on RISC-V instruction set architecture: \\
+         * Support for RV32IMC instruction set,
+         * Thirty-two 32-bit general-purpose registers,
+         * 32-bit multiplier and divider,
+         * Support for interrupts,
+         * Booted by the CPU, its dedicated timer, or RTC GPIO.
+      * ULP-FSM coprocessor - based on finite state machine:
+         * Support for common instructions, including arithmetic, jump, and program control instructions,
+         * Support for on-board sensor measurement instructions,
+         * Booted by the CPU, its dedicated timer, or RTC GPIO.
+**Wireless connectivity**
+    * **WiFi:** 802.11 b/g/n/mc (802.11n @ 2.4 GHz up to 150 Mbit/s) with simultaneous Infrastructure BSS Station mode/SoftApp mode/Promiscuous mode.
+    * **Bluetooth:**
+      * Low Energy Bluetooth 5, Bluetooth mesh,
+      * Speed 125kbps, 500 kbps, 1 Mbps, 2 Mbps,
+      * Internal sharing antenna with WiFi.
+**Memory: Internal memory:**
+      *  **ROM:** 384 kB (booting and core functions),
+      *  **SRAM:** 512 kB (for data and instruction),
+      *  **RTC SRAM:** 16 kB (for data storage and main CPU during RTC Boot from the deep-sleep mode),
+      *  **Embedded flash:**
+           * 0 MB (ESP32-S3, ESP32-S3R2, ESP32-S3R8, ESP32-S3R8V chips),
+           * 4 MB (ESP32-S3FH4R2 chip),
+           * 8 MB (ESP32-S3FN8 chip).
+      * **Embedded PSRAM:**
+           * 0 MB (ESP32-S3, ESP32-S3FN8 chips ),
+           * 2 MB (ESP32-S3R2, ESP32-S3FH4R2 chips ),
+           * 8 MB (ESP32-S3R8, ESP32-S3R8V chips ).
+**Peripheral Input/Output:**
+    * 45 programmable GPIOs,
+    * 2 × I²C (Inter-Integrated Circuit,
+    * 3 x UART (universal asynchronous receiver/transmitter),
+    * 4 × SPI (Serial Peripheral Interface),
+    * 2 × I²S (Integrated Inter-IC Sound),
+    * 1 x RMT (TX/RX),
+    * Motor PWM (pulse width modulation),
+    * LED PWM up to 8 channels,
+    * DMA controller with 5 transmit and 5 receive channels,
+    * 1 x TWAI controller compatible with CAN Spec. 2.0,
+    * 4 x pulse counters,
+    * 1 x full-speed USB OTG,
+    * 1 × USB Serial/JTAG controller,
+    * 1 x DVP 8/16 camera interface (I2S),
+    * 1 x LCD parallel interface,
+    * 1 × SD/MMC host controller.
+**Analog interfaces:**
+    * 2 x 12-bit ADCs up to 20 channels,
+    * 14 x touch sensing GPIO,
+    * 1 x temperature sensor.
+** Low power management:**
+    * Power Management Unit with five power modes,
+    * Ultra-low-power (ULP) coprocessors.
+**Security:**
+    *  Secure boot,
+    *  Flash encryption,
+    *  IEEE 802.11 standard security features are all supported, including WFA, WPA/WPA2 and WAPI,
+    *  4096-bit OTP, up to 1792-bit for customers,
+    *  Cryptographic hardware acceleration:
+      * AES-128/192/256,
+      * Hash (FIPS PUB 180-4),
+      * HMAC,
+      * RSA,
+      * Digital signature,
+      * random number generator (RNG).
+<figure esp32s3_functions>
+{{ :en:iot-open:hardware2:esp32s3block.jpg?400 | ESP32-S3 Functional block diagram}}
+<caption>ESP32-S3 Functional block diagram</caption>
+</figure>
+ESP32-S3-PICO-1 has all the functions of ESP32-S3 but integrates all peripheral components, including a crystal oscillator, decoupling capacitors, SPI flash/PSRAM, and RF matching links, within a single package. Figure {{ref>esp32s3pico_functions}} shows a functional block diagram of the ESP32-S3-PICO-1 chip.
+<figure esp32s3pico_functions>
+{{ :en:iot-open:hardware2:esp32s3picoblock.png?400 | ESP32-S3-PICO-1 Functional block diagram}}
+<caption>ESP32-S3-PICO-1 Functional block diagram</caption>
+</figure>
+== ESP32-S3 Modules ==
+The company also produces ready-made modules((https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf))((https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf))((https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-2_datasheet_en.pdf))for easier implementation in user systems. These modules combine ESP32-S2 microcontroller, antenna and additional components mounted on PCB with EM shield ((https://www.espressif.com/en/products/modules)) (table {{ref>esp32s3_modules}}):
+<table esp32s3_modules>
+<caption>Espressif ESP32-S3 modules</caption>
+^**Module**^**Chip Embedded**^**Dimensions (mm)**^**Pins**^**Flash (MB)**^**PSRAM (MB)**^**Antenna**^**Development Board**^
+|ESP32-S3-WROOM-1 (figure {{ref>esp32_s3_wroom1}}) | ESP32-S3 \\ ESP32-S3R2 \\ESP32-S3R8|18×25.5×3.1|41|4,8,16|0,2,8|PCB |ESP32-S3-DevKitC-1 \\ ESP32-S3-DevKitC-1 \\ ESP32-S3-BOX-3 \\ ESP32-S3-BOX \\ ESP32-S3-EYE \\ ESP32-S3-Korvo-1 \\ ESP32-S3-Korvo-2 \\ ESP32-S3-LCD-Ev-Board |
+|ESP32-S3-WROOM-1U| ESP32-S3 \\ ESP32-S3R2 \\ ESP32-S3R8 |18×19.2×3.2|41|4,8,16|0,2,8|IPEX |ESP32-S3-DevKitC-1|
+|ESP32-S3-WROOM-2 (figure {{ref>esp32_s3_wroom2}}) | ESP32-S3R8V  |18x25.5x3.1|41|16,32|8|PCB |ESP32-S3-DevKitC-1|
+|ESP32-S3-MINI-1 (figure {{ref>esp32_s3_mini1}})| ESP32-S3FN8 \\ ESP32-S3FH4R2|15.4×15.4×2.4|65|8| N/A |PCB|ESP32-S3-DevKitM-1|
+|ESP32-S3-MINI-1U | ESP32-S3FN8 \\ ESP32-S3FH4R2 |15.4×15.4×2.4|65|8 |N/A|IPEX|ESP32-SM-DevKitM-1|
+</table>
+<figure esp32_s3_wroom1>
+{{ :en:iot-open:hardware2:esp32s3wroom1.png?100 | ESP32-S3-Wroom-1}}
+{{ :en:iot-open:hardware2:esp32s3wroom1u.png?100 | ESP32-S3-Wroom-1U}}
+<caption>ESP32-S3-Wroom-1/1U</caption>
+</figure>
+<figure esp32_s3_wroom2>
+{{ :en:iot-open:hardware2:esp32s3wroom2.png?100 | ESP32-S3-Wroom-2}}
+<caption>ESP32-S3-Wroom-2</caption>
+</figure>
+<figure esp32_s3_mini1>
+{{ :en:iot-open:hardware2:esp32s3mini1.png?100 | ESP32-S3-Wroom-1}}
+{{ :en:iot-open:hardware2:esp32s3mini1u.png?100 | ESP32-S3-Wroom-1U}}
+<caption>ESP32-S3-Wroom-1/1U</caption>
+</figure>
+== ESP32-S3 Development Kits ==
+To facilitate the use of ESP32-S3, Espressif and other companies produce different development kits to suit different needs and present different processor functions. The original Espressif best-known small development boards are:
+  * ESP32-S3-DevkitM,
+  * ESP32-S3-DevkitC,
+  * ESP32-S3-BOX-3,
+  * ESP32-S3-BOX,
+  * ESP32-S3-EYE,
+  * ESP32-S3-Korvo-1,
+  * ESP32-S3-Korvo-2,
+  * ESP32-S3-LCD-Ev-Board.
+For this book, we present only a few of the most popular, universal for various applications development boards:
+  * ESP32-S3-DevkitM(figure {{ref>esp32_S3_devkitm}}) , \\
+  * ESP32-S3-DevkitC(figure {{ref>esp32_S3_devkitc}}) , \\
+  * Waveshare ESP32-PICO-1((https://www.waveshare.com/esp32-s3-pico.htm)) (figure {{ref>esp32_S3_pico1}}),
+  * M5Stamp-S3((https://shop.m5stack.com/products/m5stamps3-with-2-54-header-pin)) (figure {{ref>esp32_S3_stamp}}).
+<figure esp32_S3_devkitm>
+{{ :en:iot-open:hardware2:esp32-s3-devkitm-1_v1-annotated-photo_1_.png?400 | ESP32-S3-DevkitM}}
+<caption>ESP32-S3-DevkitM</caption>
+</figure>
+<figure esp32_S3_devkitc>
+{{ :en:iot-open:hardware2:esp32-s3-devkitc-1_v2-annotated-photo.png?400 | ESP32-S3-DevkitC}}
+<caption>ESP32-S3-DevkitC</caption>
+</figure>
+<figure esp32_S3_pico1>
+{{ :en:iot-open:hardware2:esp32-s3-pico-details-1.jpg?400 | Waveshare ESP32-S3-PICO-1}}
+<caption>Waveshare ESP32-S3-PICO-1</caption>
+</figure>
+<figure esp32_S3_stamp>
+{{ :en:iot-open:hardware2:m5stams3.png?200 | M5Stamp-S3 with pin headers}}
+{{ :en:iot-open:hardware2:m5stams31.png?200 | M5Stamp-S3 with pin headers}}
+<caption>M5Stamp-S3 with pin headers</caption>
+</figure>
+==ESP32-S2&S3 chip comparison==
+Table {{ref>esp32s2s3}} provides a brief comparison of the most essential features of the ESP32-S2 & ESP32-S3  systems((https://docs.espressif.com/projects/esp-idf/en/v5.0/esp32/hw-reference/chip-series-comparison.html))
+<table esp32s2s3>
+<caption>ESP32-S2 & ESP32-S3 family brief comparison</caption>
+^**Feature**^**ESP32 Series**^**ESP32-S2 Series**^**ESP32-S3 Series**^
+|Launch year|2016|2020|2020|
+|Core|Xtensa® dual-/single core 32-bit LX6|Xtensa® single-core 32-bit LX7|Xtensa® dual-core 32-bit LX7|
+|Wi-Fi protocols|802.11 b/g/n, 2.4 GHz|802.11 b/g/n, 2.4 GHz|802.11 b/g/n, 2.4 GHz|
+|Bluetooth®|Bluetooth v4.2 BR/EDR and Bluetooth Low Energy|✖️|Bluetooth 5.0|
+|Typical frequency|240 MHz (160 MHz for ESP32-S0WD)|240 MHz|240 MHz|
+|SRAM|520 KB|320 KB|512 KB|
+|ROM|448 KB for booting and core functions|128 KB for booting and core functions|384 KB for booting and core functions|
+|Embedded flash|2 MB, 4 MB, or none, depending on variants|2 MB, 4 MB, or none, depending on variants|8 MB or none, depending on variants|
+|External flash|Up to 16 MB device, address 11 MB + 248 KB each time|Up to 1 GB device, address 11.5 MB each time|Up to 1 GB device, address 32 MB each time|
+|External RAM|Up to 8 MB device, address 4 MB each time|Up to 1 GB device, address 11.5 MB each time|Up to 1 GB device, address 32 MB each time|
+|Cache|✔️ Two-way set associative|✔️ Four-way set associative, independent instruction cache and data cache|✔️ Four-way or eight-way set associative for instruction cache; four-way set associative for data cache, 32-bit data/instruction bus width|
+|**Peripherals**|  |  |  |
+|ADC|Two 12-bit, 18 channels|Two 12-bit, 20 channels|Two 12-bit SAR ADCs, 20 channels|
+|DAC|Two 8-bit channels|Two 8-bit channels|✖️|
+|Timers|Four 64-bit general-purpose timers, and three watchdog timers|Four 64-bit general-purpose timers, and three watchdog timers|Four 54-bit general-purpose timers, and three watchdog timers|
+|Temperature sensor|✖️|1|1|
+|Touch sensor|10|14|14|
+|Hall sensor|1|✖️|✖️|
+|GPIO|34|43|45|
+|SPI|4|4|4|
+|LCD interface|1|1|1|
+|UART|3|2 <sup>1</sup>|3|
+|I2C|2|2|2|
+|I2S|2, can be configured to operate with 8/16/32/40/48-bit resolution as an input or output channel.|1, can be configured to operate with 8/16/24/32/48/64-bit resolution as an input or output channel.|2, can be configured to operate with 8/16/24/32-bit resolution as an input or output channel.|
+|Camera interface|1|1|1|
+|DMA|Dedicated DMA to UART, SPI, I2S, SDIO slave, SD/MMC host, EMAC, BT, and Wi-Fi|Dedicated DMA to UART, SPI, AES, SHA, I2S, and ADC Controller|General-purpose, 5 TX channels, 5 RX channels|
+|RMT|8 channels|4 channels <sup>1</sup>, can be configured to TX/RX channels|8 channels <sup>2</sup>, 4 TX channels, 4 RX channels|
+|Pulse counter|8 channels|4 channels <sup>1</sup>|4 channels <sup>1</sup>|
+|LED PWM|16 channels|8 channels <sup>1</sup>|8 channels <sup>1</sup>|
+|MCPWM|2, six PWM outputs|✖️|2, six PWM outputs|
+|USB OTG|✖️|1|1|
+|TWAI® controller (compatible with ISO 11898-1)|1|1|1|
+|SD/SDIO/MMC host controller|1|✖️|1|
+|SDIO slave controller|1|✖️|✖️|
+|Ethernet MAC|1|✖️|✖️|
+|ULP|ULP FSM|PicoRV32 core with 8 KB SRAM, ULP FSM|PicoRV32 core with 8 KB SRAM, ULP FSM|
+|Debug Assist|✖️|✖️|✖️|
+|**Security**|  |  |  |
+|Secure boot|✔️|✔️ Faster and safer, compared with ESP32|✔️ Faster and safer, compared with ESP32|
+|Flash encryption|✔️|✔️ Support for PSRAM encryption. Safer, compared with ESP32|✔️ Support for PSRAM encryption. Safer, compared with ESP32|
+|OTP|1024-bit|4096-bit|4096-bit|
+|AES|✔️ AES-128, AES-192, AES-256 (FIPS PUB 197)|✔️ AES-128, AES-192, AES-256 (FIPS PUB 197); DMA support|✔️ AES-128, AES-256 (FIPS PUB 197); DMA support|
+|HASH|SHA-1, SHA-256, SHA-384, SHA-512 (FIPS PUB 180-4)|SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); DMA support|SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256, SHA-512/t (FIPS PUB 180-4); DMA support|
+|RSA|Up to 4096 bits|Up to 4096 bits|Up to 4096 bits|
+|RNG|✔️|✔️|✔️|
+|HMAC|✖️|✔️|✔️|
+|Digital signature|✖️|✔️|✔️|
+|XTS|✖️|✔️ XTS-AES-128, XTS-AES-256|✔️ XTS-AES-128, XTS-AES-256|
+|**Other**|  |  |  |
+|Deep-sleep (ULP sensor-monitored pattern)|100 μA (when ADC work with a duty cycle of 1%)|22 μA (when touch sensors work with a duty cycle of 1%)|TBD|
+|Size|QFN48 5*5, 6*6, depending on variants|QFN56 7*7|QFN56 7*7|
+  -  **Note** 1: Reduced chip area compared with ESP32 \\
+  -  **Note** 2: Reduced chip area compared with ESP32 and ESP32-S2 \\
+  -  **Note** 3: Die size: ESP32-S2 < ESP32-S3 < ESP32 \\
+</table>