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| ====== Processor Taxonomies, SISD, SIMD, MIMD ====== | ====== Processor Taxonomies, SISD, SIMD, MIMD ====== |
| As we already know, the processor executes instructions which can process the data. We can consider two streams flowing through the processor. A stream of instructions which passes through the control unit, and a stream of data processed by the execution unit. In 1966, Michael Flynn proposed the taxonomies to define different processors' architectures. Flynn classification is based on the number of concurrent instruction (or control) streams and data streams available in the architecture. | As we already know, the processor executes instructions that process data. We can consider two streams flowing through the processor. A stream of instructions which passes through the control unit, and a stream of data processed by the execution unit. In 1966, Michael Flynn proposed the taxonomies to define different processors' architectures. Flynn classification is based on the number of concurrent instruction (or control) streams and data streams available in the architecture. |
| Taxonomies as proposed by Flynn are presented in Table{{ref>taxonomies}} | Taxonomies as proposed by Flynn are presented in Table{{ref>taxonomies}} |
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| ===== SISD ===== | ===== SISD ===== |
| Single Instruction Single Data processor is a classical processor with a single control unit and a single execution unit. It can fetch a single instruction at one cycle and perform single calculation. Mature PC computers based on 8086, 80286 or 80386 processors or some modern small-scale microcontrollers like AVR are examples of such an architecture. | Single Instruction Single Data processor is a classical processor with a single control unit and a single execution unit. It can fetch a single instruction in one cycle and perform a single calculation. Mature PC computers based on 8086, 80286 or 80386 processors or some modern small-scale microcontrollers like AVR, are examples of such an architecture. |
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| ===== SIMD ===== | ===== SIMD ===== |
| Single Instruction Multiple Data is an architecture in which one instruction stream can perform calculations on multiple data streams. Good examples of implementation of such architecture are all vector instructions (called also SIMD instructions) like MMX, SSE, AVX, and 3D-Now in x64 Intel and AMD processors. Modern ARM processors also implement SIMD instructions which perform vectorised operations. | Single Instruction Multiple Data is an architecture in which one instruction stream can perform calculations on multiple data streams. Good examples of implementing such an architecture are the vector instructions (also called SIMD instructions) such as MMX, SSE, AVX, and 3D-Now on x64 Intel and AMD processors. Modern ARM processors also implement SIMD instructions, which perform vectorised operations. |
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| ===== MIMD ===== | ===== MIMD ===== |
| Multiple Instruction Multiple Data is an architecture in which many control units operate on multiple streams of data. These are all architectures with more than one processor (multi-processor architectures). MIMD architectures include multi-core processors like modern x64, ARM and even ESP32 SoCs. This also includes supercomputers and distributed systems, using common shared memory or even a distributed but shared memory. | Multiple Instruction Multiple Data is an architecture in which many control units operate on multiple data streams. These are all architectures with more than one processor (multi-processor architectures). MIMD architectures include multi-core processors such as modern x64, ARM, and even ESP32 SoCs. This also includes supercomputers and distributed systems, using common shared memory or even a distributed but shared memory. |
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| ===== MISD ===== | ===== MISD ===== |
| Multiple Instruction Single Data. At first glance, they seem illogical, but these are machines where the certainty of correct calculations is crucial and required for the security of the system operation. Such an approach can be found in applications like space shuttle computers. | Multiple Instruction Single Data. At first glance, it seems illogical, but in these machines, the certainty of correct calculations is crucial to the security of system operation. Such an approach can be found in applications like space shuttle computers. |
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| ===== SIMT ===== | ===== SIMT ===== |
| Single Instruction Multiple Threads. Originally defined as the subset of SIMD. In modern construction, Nvidia uses this execution model in their G80 architecture | Single Instruction Multiple Threads. Originally defined as the subset of SIMD. The difference between SIMD and SIMT is that in pure SIMD, a single instruction operates on all elements of the vector in the same way. In SIMT, selected threads can be activated or deactivated. Instructions and data are processed only on the active threads, while the data remains unchanged on inactive threads. |
| ((https://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf)) where multiple independent threads execute concurrently using a single instruction. | |
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| | We can find SIMT in modern constructions. NVIDIA uses this execution model in their G80 architecture |
| | ((https://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf)), where multiple independent threads execute concurrently using a single instruction. |
| | In the x64 architecture, the new vector instructions have masked variants, in which an operation can be enabled or disabled for selected vector elements. This is done using an additional operand called a mask or a predicate. |
