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en:multiasm:piot:chapter_4_5 [2026/02/17 15:19] – ToDo checked: Marcin, czy tu nie brakuje rysunku? jtokarzen:multiasm:piot:chapter_4_5 [2026/02/19 18:10] (current) – jtokarz
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 +====== Addressing Modes ======
  
 +Addressing modes define how the processor accesses data. There are 15 different addressing modes, such as: Direct Addressing, Indirect Addressing, Indirect with Displacement, Immediate Addressing, Register Addressing, Relative Addressing, Indirect I/O Addressing, and Stack Addressing.
 +
 +Details on addressing modes are presented in Fig. {{ref>avr_addr_1}},{{ref>avr_addr_2}},{{ref>avr_addr_3}},{{ref>avr_addr_4}},{{ref>avr_addr_5}},{{ref>avr_addr_6}},{{ref>avr_addr_7}},{{ref>avr_addr_8}},{{ref>avr_addr_9}},{{ref>avr_addr_10}},{{ref>avr_addr_11}},{{ref>avr_addr_12}},{{ref>avr_addr_13}},{{ref>avr_addr_14}} and {{ref>avr_addr_15}}:
 +
 +**1. Direct Single Register Addressing**
 +
 +<figure avr_addr_1>
 +{{ :en:multiasm:piot:ad01.png |Direct Single Register Addressing}}
 +<caption>Direct Single Register Addressing</caption>
 +</figure>
 +
 +The operand is contained in the destination register (Rd).
 +
 +**2. Direct Register Addressing, Two Registers**
 +
 +<figure avr_addr_2>
 +{{ :en:multiasm:piot:ad02.png |Direct Register Addressing, Two Registers}}
 +<caption>Direct Register Addressing, Two Registers</caption>
 +</figure>
 +
 +Operands are contained in the source register (Rr) and destination register (Rd). The result is stored in the destination register (Rd).
 + 
 +**3. I/O Direct Addressing**
 +
 +<figure avr_addr_3>
 +{{ :en:multiasm:piot:ad03.png |I/O Direct Addressing}} 
 +<caption>I/O Direct Addressing</caption>
 +</figure>
 +
 +Operand address A is contained in the instruction word. Rr/Rd specifies the destination or source register.
 +
 +**4. Data Direct Addressing**
 +
 +<figure avr_addr_4>
 +{{ :en:multiasm:piot:ad04.png |Data Direct Addressing}}  
 +<caption>Data Direct Addressing</caption>
 +</figure>
 +
 +A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. The LDS instruction uses the RAMPD register to access memory above 64 KB.
 +
 +**5. Data Indirect Addressing**
 +
 +<figure avr_addr_5>
 +{{ :en:multiasm:piot:ad05.png |Data Indirect Addressing}}
 +<caption>Data Indirect Addressing</caption>
 +</figure>
 +
 +The operand address is the contents of the X-, Y-, or Z-pointer. In AVR devices without SRAM, Data Indirect Addressing is called Register Indirect Addressing.
 +
 +**6. Data Indirect Addressing with Pre-decrement**
 +
 +<figure avr_addr_6>
 +{{ :en:multiasm:piot:ad06.png |Data Indirect Addressing with Pre-decrement}}  
 +<caption>Data Indirect Addressing with Pre-decrement</caption>
 +</figure>
 +
 +The X,- Y-, or the Z-pointer is decremented before the operation. The operand address is the decremented contents of the X-, Y-, or Z-pointer.
 +
 +**7. Data Indirect Addressing with Post-increment**
 +
 +<figure avr_addr_7>
 +{{ :en:multiasm:piot:ad07.png |Data Indirect Addressing with Post-increment}}
 +<caption>Data Indirect Addressing with Post-increment</caption>
 +</figure>
 +
 +The X-, Y-, or Z-pointer is incremented after the operation. The operand address is the content of the X-, Y-, or Z-pointer before incrementing.
 +
 +**8. Data Indirect with Displacement**
 +
 +<figure avr_addr_8>
 +{{ :en:multiasm:piot:ad08.png |Data Indirect with Displacement}}
 +<caption>Data Indirect with Displacement</caption>
 +</figure>
 +
 +The operand address is the result of the q displacement contained in the instruction word added to the Y- or Z-pointer. Rd/Rr specify the destination or source register.
 +
 +**9. Program Memory Constant Addressing**
 +
 +<figure avr_addr_9>
 +{{ :en:multiasm:piot:ad09.png |Program Memory Constant Addressing}}
 +<caption>Program Memory Constant Addressing</caption>
 +</figure>
 +
 +The byte address in program memory is determined by the value stored in the Z-pointer.
 +
 +The upper 15 bits (Most Significant bits - MSbs) select the word address (each word contains 2 bytes).
 +
 +The lowest bit (Less Significant bit - LSb) selects which byte of that word is used:
 +
 +  * 0 → low byte,
 +
 +  * 1 → high byte.
 +
 +For the SPM instruction, the LSb must be 0, because SPM works on whole words. SPM (Store Program Memory) is an instruction used in AVR microcontrollers to write data into program memory (Flash). Normally, Flash is read‑only during program execution, but SPM allows the microcontroller to modify or update its own program, for example inside a bootloader.
 +
 +
 +When the ELPM instruction is used, the RAMPZ register provides extra address bits so the processor can access larger program memories.
 +ELPM (Extended Load Program Memory) is an instruction used to read bytes from program memory when the memory is larger than 64 KB.
 +The normal LPM instruction can only access 64 KB because it uses the 16‑bit Z register.
 +ELPM adds extra address bits from the RAMPZ register, allowing access to extended program memory on larger AVR devices.
 +
 +In short:
 +ELPM = LPM with support for large program memory using RAMPZ.
 +
 +
 +**10. Program Memory Addressing with Post-increment**
 +<todo @pczekalski>Continue figures formatting here</todo>
 +<todo @mfojcik #jtokarz:2026-02-17>Marcin, czy tu nie brakuje rysunku?</todo>
 +
 +<figure avr_addr_10>
 +{{ :en:multiasm:piot:ad10.png |Program Memory Addressing with Post-increment}}
 +<caption>Program Memory Addressing with Post-increment</caption>
 +</figure>
 +
 +The Z-pointer contents specify a constant byte address. The 15 MSbs select the word address. The LSb selects the low byte if cleared (LSb == 0) or the high byte if set (LSb == 1). If ELPM Z+ is used, the RAMPZ Register is used to extend the Z-register.
 +
 +**11. Store Program Memory**
 +<todo @mfojcik>Marcin, tu mam wątpliwości co do nazwy tego rozdziału - to addressing mode?</todo>
 +<figure avr_addr_11>
 +{{ :en:multiasm:piot:ad11.png |Store Program Memory}}
 +<caption>Store Program Memory</caption>
 +</figure>
 +
 +The Z-pointer is incremented by 2 after the operation. The Z-pointer contents specify a constant byte address before incrementing. The 15 MSbs select the word address, and the LSb should be left cleared.
 +
 +**12. Direct Program Memory Addressing**
 +
 +<figure avr_addr_12>
 +{{ :en:multiasm:piot:ad12.png |Direct Program Memory Addressing}}
 +<caption>Direct Program Memory Addressing</caption>
 +</figure>
 +
 +Program execution continues at the address immediate in the instruction word.
 +<todo @mfojcik> "immediate" -> "following immediately the instruction word"?</todo>
 +
 +**13. Indirect Program Memory Addressing**
 +
 +<figure avr_addr_13>
 +{{ :en:multiasm:piot:ad13.png |Indirect Program Memory Addressing}}
 +<caption>Indirect Program Memory Addressing</caption>
 +</figure>
 +
 +Program execution continues at the address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).
 +
 +**14. Extended Indirect Program Memory Addressing**
 +
 +<figure avr_addr_14>
 +{{ :en:multiasm:piot:ad14.png |Extended Indirect Program Memory Addressing}}
 +<caption>Extended Indirect Program Memory Addressing</caption>
 +</figure>
 +
 +Program execution continues at the address contained by the Z-register and the EIND-register (i.e., the PC is loaded with the contents of the EIND and Z-register).
 +
 +**15. Relative Program Memory Addressing**
 +
 +<figure avr_addr_15>
 +{{ :en:multiasm:piot:ad15.png |Relative Program Memory Addressing}}
 +<caption>Relative Program Memory Addressing</caption>
 +</figure>
 +
 +Program execution continues at the address PC + k + 1. The relative address k is from -2048 to 2047.
en/multiasm/piot/chapter_4_5.txt · Last modified: 2026/02/19 18:10 by jtokarz
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